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【文档书籍】 Reddy V. Recent Trends in VLSI and Semiconductor Packaging 2025

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Reddy V. Recent Trends in VLSI and Semiconductor Packaging 2025.pdf 114.8 MB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - VSDOpen2020 - VLSI online conference.zip

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[ FreeCourseWeb.com ] Udemy - VSDOpen2020 - VLSI online conference.zip 2.2 GB

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【影视】 ASIC Bootcamp for VLSI Engineer STA Basic Concepts [UdemyCourseDownloader]

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03. Delay Calculation/1. Delay Calculation.mp4 595.3 MB
05. Timing Verification/1. Timing Verification.mp4 581.4 MB
04. Constraints Develop/1. Constraints Develop.mp4 430.7 MB
06. Special Timing Checks/1. Special Timing Checks.mp4 323.2 MB
02. STA Definition/1. What is STA.mp4 305.7 MB
09. Sign-off Checklist/1. Sign-off Checklist.mp4 158.8 MB
08. STA Methodology/1. STA Methodology.mp4 157.4 MB
07. Crosstalk & Noise/1. Crosstalk & Noise.mp4 106.8 MB
01. Introduction/1. Course Information.mp4 90.3 MB
05. Timing Verification/2.1 Chapter 4.pptx.pptx 2.6 MB
03. Delay Calculation/2.1 Chapter 2.pptx.pptx 2.6 MB
06. Special Timing Checks/2.1 Chapter 5.pptx.pptx 2.5 MB
04. Constraints Develop/2.1 Chapter 3.pptx.pptx 2.1 MB
10. Resources/1.1 STA Basic Concepts.pdf.pdf 1.3 MB
02. STA Definition/2.1 Chapter 1.pptx.pptx 1.1 MB
08. STA Methodology/2.1 Chapter 7.pptx.pptx 642.2 kB
07. Crosstalk & Noise/2.1 Chapter 6.pptx.pptx 318.2 kB
09. Sign-off Checklist/2.1 Chapter 8.pptx.pptx 112.7 kB
01. Introduction/1.2 Chapter 0.pptx.pptx 95.3 kB
01. Introduction/1.1 Resume Template.docx.docx 27.1 kB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - VLSI Digital Design using Verilog and hardware- Handson_temp.zip

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[ FreeCourseWeb.com ] Udemy - VLSI Digital Design using Verilog and hardware- Handson_temp.zip 8.6 GB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - ASIC Bootcamp for VLSI Engineer- STA Basic Concepts (Updated 1-2020).zip

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[ FreeCourseWeb.com ] Udemy - ASIC Bootcamp for VLSI Engineer- STA Basic Concepts (Updated 1-2020).zip 2.3 GB

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【音乐】 Monolake - VLSI (2016)(FLAC)(CD)

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Monolake - VLSI.m3u 680 Bytes
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07 - Monolake - Error.flac 18.3 MB
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10 - Monolake - Nmos.flac 30.0 MB
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11 - Monolake - Glypnir.flac 40.6 MB
05 - Monolake - Geometry Engine.flac 48.9 MB

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【影视】 coursera-vlsi-cad-logic-to-layout

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Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.txt 2.6 kB
Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.srt 4.1 kB
Lectures/11_Tools/03_Espresso_Tutorial_Video_3-06.mp4 5.3 MB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.txt 5.2 kB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.srt 7.9 kB
Lectures/11_Tools/02_MiniSat_Tutorial_Video_6-11.mp4 10.1 MB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.txt 4.2 kB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.srt 6.3 kB
Lectures/11_Tools/01_KBDD_Tutorial_Video_5-20.mp4 7.3 MB
Lectures/01_Orientation/01_Course_Promo_Video.mp4 2.7 MB
Assignements/Final Exam/0_Final_Exam.png 1.4 MB
Lectures/04_BDDs_SAT_Week_2/02_Lecture_3.2-_BDD_Basics_Part_2_16-51.srt 22.3 kB
Lectures/04_BDDs_SAT_Week_2/04_Lecture_3.4-_BDD_Ordering_28-12.txt 25.5 kB
Lectures/04_BDDs_SAT_Week_2/07_Lecture_4.3-_Sat_For_Logic_25-45.mp4 30.1 MB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.txt 16.6 kB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.srt 25.4 kB
Lectures/04_BDDs_SAT_Week_2/06_Lecture_4.2-_Sat_Part_2_17-56.mp4 23.4 MB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.txt 14.0 kB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.srt 21.1 kB
Lectures/04_BDDs_SAT_Week_2/05_Lecture_4.1-_SAT_Part_1_13-51.mp4 19.4 MB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - VSDOpen2018 - First ever online VLSI conference.zip

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[ FreeCourseWeb.com ] Udemy - VSDOpen2018 - First ever online VLSI conference.zip 3.0 GB

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【影视】 [ DevCourseWeb.com ] Udemy - VLSI - Essential concepts and detailed interview guide

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~Get Your Files Here !/01 - Physical Design Flow Overview/004 Route - DRC Clean - Parasitics Extraction - Final STA.mp4 111.2 MB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/002 Design Rule Check.mp4 104.3 MB
~Get Your Files Here !/03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4 95.8 MB
~Get Your Files Here !/16 - Routing And Design Rule Check (DRC)/001 Introduction To Maze Routing - Lee's Algorithm.mp4 92.5 MB
~Get Your Files Here !/03 - Placement/003 Optimize Placement Continued.mp4 91.2 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/004 Data Slew Check.mp4 86.9 MB
~Get Your Files Here !/17 - Parasitics Extraction/001 Introduction To IEEE 1481-1999 SPEF Format.mp4 82.4 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/003 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4 76.4 MB
~Get Your Files Here !/15 - Noise Protection Technique/003 Drive Strength.mp4 70.9 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization.mp4 68.7 MB
~Get Your Files Here !/08 - Buffered H-Tree/004 H-Tree Clock Buffers And Pulse Width Check.mp4 68.6 MB
~Get Your Files Here !/08 - Buffered H-Tree/003 CMOS Inverter PMOSNMOS Matching Switching Resistance Solution.mp4 66.8 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/003 Clock Net Shielding.mp4 65.8 MB
~Get Your Files Here !/08 - Buffered H-Tree/001 H-Tree Buffering Observations.mp4 63.4 MB
~Get Your Files Here !/08 - Buffered H-Tree/005 Dynamic Power And Short Circuit Power.mp4 61.1 MB
~Get Your Files Here !/11 - Introduction To Crosstalk - Why and How Crosstalk occurs in a CHIP/002 Dominant Lateral Capacitance.mp4 60.0 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/003 Impact Of Unbalanced Skew On Hold Time.mp4 58.5 MB
~Get Your Files Here !/06 - H-Tree/003 H-Tree Latency And Power Check.mp4 58.3 MB
~Get Your Files Here !/10 - Static Timing Analysis With Real Clocks/002 Impact Of Unbalanced Skew On Setup Time.mp4 55.3 MB
~Get Your Files Here !/06 - H-Tree/002 H-Tree Pulse Width And Duty Cycle Check.mp4 50.8 MB

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【影视】 [ DevCourseWeb.com ] Udemy - Digital Timing Basics For Vlsi Interview and Soc Design

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~Get Your Files Here !/7 - Frequency vs Voltage in SoC/30 - FV Curve Explanation.mp4 69.2 MB
~Get Your Files Here !/4 - Problem Solving for Interview/15 - Setup Violation Fix Clock Path Delay.mp4 56.2 MB
~Get Your Files Here !/3 - Static Timing Foundation/12 - Example for Setup & Hold Condition.mp4 50.0 MB
~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/38 - Maximum Frequency of Operation with Clock Skew.mp4 40.1 MB
~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/23 - Clock Gating Setup & Hold Time.mp4 39.6 MB
~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/21 - Positive Latch Setup & Hold Time.mp4 38.3 MB
~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/24 - Negative Hold Time for Flop.mp4 36.7 MB
~Get Your Files Here !/4 - Problem Solving for Interview/19 - Latency Reduction with Optimized Design.mp4 36.6 MB
~Get Your Files Here !/3 - Static Timing Foundation/11 - Hold Time Condition in Cycle Path.mp4 32.2 MB
~Get Your Files Here !/4 - Problem Solving for Interview/18 - Good Margin but Higher Latency.mp4 31.8 MB
~Get Your Files Here !/1 - Introduction/1 - Introduction.mp4 31.0 MB
~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/25 - Negative Setup Time for Flop.mp4 27.6 MB
~Get Your Files Here !/4 - Problem Solving for Interview/14 - Setup Violation.mp4 25.7 MB
~Get Your Files Here !/3 - Static Timing Foundation/10 - Setup Time Condition in Cycle Path.mp4 25.2 MB
~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/22 - Negative Latch Setup & Hold Time.mp4 24.9 MB
~Get Your Files Here !/4 - Problem Solving for Interview/17 - Hold Violation Fix Data Path Delay.mp4 20.0 MB
~Get Your Files Here !/4 - Problem Solving for Interview/13 - Setup & Hold Margin Computation.mp4 19.7 MB
~Get Your Files Here !/4 - Problem Solving for Interview/20 - Design Issues in Real World SoC.mp4 19.0 MB
~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/33 - Multiple Path Hold Time Analysis.mp4 18.6 MB
~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/32 - Multiple Path Setup Time Analysis.mp4 18.2 MB

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【文档书籍】 [ CourseWikia.com ] Nanoscale VLSI - Devices, Circuits and Applications

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~Get Your Files Here !/9811579369.epub 70.0 MB
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【其他】 VLSI Academy - Circuit Design & SPICE Simulations

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VLSI Academy - Circuit Design & SPICE Simulations.tgz 409.1 MB
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【文档书籍】 Sze S. VLSI technology 1983

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Sze S. VLSI technology 1983.pdf 115.1 MB

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【音乐】 Monolake - VLSI (2016) FLAC

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Monolake - Dystopia.flac 33.8 MB
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【其他】 VLSI Academy - Clock Tree Synthesis

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - Become Zero to Hero in vlsi design [comprehensive video].zip

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[ FreeCourseWeb.com ] Udemy - Become Zero to Hero in vlsi design [comprehensive video].zip 2.9 GB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - VLSI Course Series - FPGA Architecture Basics.zip

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[ FreeCourseWeb.com ] Udemy - VLSI Course Series - FPGA Architecture Basics.zip 258.6 MB

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【文档书籍】 [ CourseMega.com ] Digital Integrated Circuit Design - From VLSI Architectures to CMOS Fabrication (Solution Manual, Solutions)

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~Get Your Files Here !/Lectures/A_Primer_on_CMOS_Technology.pdf 7.1 MB
~Get Your Files Here !/Lectures/From_Algorithms_to_Architectures.pdf 6.2 MB
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~Get Your Files Here !/Lectures/17-Gate-_and_Transistor-Level_Design.pdf 3.4 MB
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~Get Your Files Here !/Lectures/Modelling_Hardware_with_VHDL.pdf 2.9 MB
~Get Your Files Here !/Lectures/15-VLSI_Economics_and_Project_Management.pdf 2.6 MB
~Get Your Files Here !/Lectures/16-Energy_Efficiency_and_Heat_Removal.pdf 2.3 MB
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~Get Your Files Here !/Lectures/VLSI_Economics_and_Project_Management.pdf 2.1 MB
~Get Your Files Here !/Lectures/20-Clocking_of_Synchronous_Circuits.pdf 1.9 MB
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~Get Your Files Here !/Lectures/Clocking_of_Synchronous_Circuits.pdf 1.6 MB
~Get Your Files Here !/Lectures/21-Acquisition_of_Asynchronous_Data.pdf 1.3 MB
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【文档书籍】 Babu H. VLSI Circuits and Embedded Systems 2022

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Babu H. VLSI Circuits and Embedded Systems 2022.pdf 122.0 MB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - VLSI - Design For Test (DFT)- JTAG, Boundary SCAN and IJTAG.zip

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[ FreeCourseWeb.com ] Udemy - VLSI - Design For Test (DFT)- JTAG, Boundary SCAN and IJTAG.zip 544.4 MB

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