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【影视】 [ CourseBoat.com ] Udemy - Designing Digital Systems Using VHDL - An introduction

收录时间:2022-01-09 文档个数:246 文档大小:3.5 GB 最近下载:2025-05-16 人气:5994 磁力链接

~Get Your Files Here !/4. Start of simulation and design/11. Changing the names of the signals.mp4 136.8 MB
~Get Your Files Here !/4. Start of simulation and design/18. Seneric inside NTT.mp4 130.1 MB
~Get Your Files Here !/4. Start of simulation and design/9. Test Bench Types.mp4 117.3 MB
~Get Your Files Here !/4. Start of simulation and design/16. Demultiplexter.mp4 101.4 MB
~Get Your Files Here !/4. Start of simulation and design/27. Type Conversion Simulation.mp4 97.4 MB
~Get Your Files Here !/4. Start of simulation and design/21. Generic Example.mp4 75.1 MB
~Get Your Files Here !/4. Start of simulation and design/22. ISE Library Section.mp4 73.5 MB
~Get Your Files Here !/2. basic concepts of digital/7. Sequential logic idea.mp4 71.7 MB
~Get Your Files Here !/4. Start of simulation and design/7. Designing the Gate Level.mp4 70.1 MB
~Get Your Files Here !/4. Start of simulation and design/14. BCD code to Excess-3.mp4 61.2 MB
~Get Your Files Here !/3. tips to use ISE/16. ISE warnings.mp4 57.3 MB
~Get Your Files Here !/4. Start of simulation and design/26. Type Conversion in ISE.mp4 51.5 MB
~Get Your Files Here !/2. basic concepts of digital/52. Synchronous vs Asynchronous.mp4 50.8 MB
~Get Your Files Here !/3. tips to use ISE/14. ISE Schematic.mp4 48.8 MB
~Get Your Files Here !/3. tips to use ISE/8. FIFO operation.mp4 47.6 MB
~Get Your Files Here !/3. tips to use ISE/13. Synthesize.mp4 46.5 MB
~Get Your Files Here !/3. tips to use ISE/15. ISE Signals.mp4 46.3 MB
~Get Your Files Here !/3. tips to use ISE/12. ISE Design properties.mp4 46.1 MB
~Get Your Files Here !/2. basic concepts of digital/2. Basic Concepts of Digital.mp4 45.0 MB
~Get Your Files Here !/3. tips to use ISE/9. General Purpose processor.mp4 41.1 MB

猜你喜欢： VHDL introduction Designing Udemy CourseBoat Systems Digital Using com

【影视】 [ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)

收录时间:2022-01-29 文档个数:53 文档大小:3.2 GB 最近下载:2025-05-16 人气:2831 磁力链接

~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4 489.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4 323.1 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4 308.1 MB
~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4 238.9 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4 209.8 MB
~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4 205.8 MB
~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4 199.4 MB
~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4 198.7 MB
~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4 166.1 MB
~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4 163.5 MB
~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4 152.4 MB
~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4 134.6 MB
~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4 122.1 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4 116.6 MB
~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp4 93.2 MB
~Get Your Files Here !/1. Introduction/1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf 12.8 MB
~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx 3.4 MB
~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx 3.0 MB
~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx 2.6 MB
~Get Your Files Here !/12. Processor Design and its VHDL/1.6 Exercises_set1_solution_part2.pdf 2.5 MB

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【影视】 [ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)

收录时间:2025-02-13 文档个数:22 文档大小:2.7 GB 最近下载:2025-05-15 人气:1068 磁力链接

~Get Your Files Here !/18 -888.mp4 461.5 MB
~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4 304.8 MB
~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4 261.9 MB
~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4 203.3 MB
~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4 176.0 MB
~Get Your Files Here !/17 -the cache control.mp4 171.0 MB
~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4 150.4 MB
~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4 128.1 MB
~Get Your Files Here !/13 -how to connect different units using the control.mp4 127.9 MB
~Get Your Files Here !/19 -top wiring and conclusion.mp4 110.6 MB
~Get Your Files Here !/3 -accessing resource file.mp4 110.4 MB
~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4 101.4 MB
~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4 86.8 MB
~Get Your Files Here !/11 -architecture of a register bank.mp4 72.5 MB
~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4 54.7 MB
~Get Your Files Here !/10 -How to design a simple ALU.mp4 49.2 MB
~Get Your Files Here !/2 -Architecture of the design.mp4 47.9 MB
~Get Your Files Here !/4 -How to design the program memory.mp4 39.5 MB
~Get Your Files Here !/1 -Introduction.mp4 21.2 MB
~Get Your Files Here !/3 -class_resources.zip 11.6 MB

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【影视】 [FreeTutorials.Us] Udemy - Learn VHDL and FPGA Development

收录时间:2018-09-14 文档个数:237 文档大小:2.1 GB 最近下载:2025-05-12 人气:1395 磁力链接

10. Xilinx Tools/1.1 Digilent Inc. - Digital Design Engineer's Source.html 208 Bytes
10. Xilinx Tools/1.2 Xilinx ISE Download.html 158 Bytes
10. Xilinx Tools/1. Xilinx Tools Introduction.mp4 1.4 MB
10. Xilinx Tools/1. Xilinx Tools Introduction.srt 1.3 kB
10. Xilinx Tools/1. Xilinx Tools Introduction.vtt 1.2 kB
10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.mp4 38.7 MB
10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.srt 9.1 kB
10. Xilinx Tools/2. Download the Vivado Tool Suite for the BASYS 3.vtt 8.0 kB
10. Xilinx Tools/3. ISim VHDL Simulation Tool.mp4 4.9 MB
10. Xilinx Tools/3. ISim VHDL Simulation Tool.srt 2.7 kB
10. Xilinx Tools/3. ISim VHDL Simulation Tool.vtt 2.3 kB
10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.mp4 9.7 MB
10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.srt 9.0 kB
10. Xilinx Tools/4. Xilinx ISE FPGA Development Tool.vtt 7.9 kB
10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.mp4 1.9 MB
10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.srt 2.1 kB
10. Xilinx Tools/5. Programming The BASYS 2 FPGA Development Board.vtt 1.8 kB
10. Xilinx Tools/6. Xilinx Tools.html 163 Bytes
11. Lab 1 - Full Adder/1.1 Lab-1.zip.zip 6.9 kB
11. Lab 1 - Full Adder/1. Introduction.mp4 6.0 MB

猜你喜欢： Development VHDL FPGA FreeTutorials Us Udemy Learn

【影视】 Get Started with VHDL Programming Design Your Own Hardware

收录时间:2021-03-23 文档个数:90 文档大小:1.1 GB 最近下载:2025-05-15 人气:4287 磁力链接

[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/6. VHDL Program Structure/1. VHDL Program Structure.mp4 119.0 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/13. Difference between Signals and Variables in VHDL/1. Difference between Signals and Variables in VHDL.mp4 112.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/14. Wait on and Wait Until in VHDL/1. Wait on and Wait Until in VHDL.mp4 81.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/15. Conditional Statements In VHDL IF THEN ELSIF ELSE/1. Conditional Statements In VHDL IF THEN ELSIF ELSE.mp4 64.2 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/7. Extra/1. Download and Install.mp4 58.0 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/16. Sensitivity List in VHDL/1. Create a Process with A Sensitivity List in VHDL.mp4 57.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/17. Std_logic Datatype/1. Std_logic Datatype.mp4 54.7 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/13. Difference between Signals and Variables in VHDL/2. Test the Difference between Signals and Variables in VHDL.mp4 53.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/15. Conditional Statements In VHDL IF THEN ELSIF ELSE/2. Test Conditional Statements In VHDL.mp4 39.6 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/8. Write Your First VHDL Code/1. Write Your First VHDL Code.mp4 37.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/17. Std_logic Datatype/2. Simple Test Std_logic DataType.mp4 37.8 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/5. VHDL Design Flow/1. VHDL Design Flow.mp4 36.8 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/14. Wait on and Wait Until in VHDL/2. Test Wait on and Wait Until in VHDL.mp4 33.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/10. Loop and Exit in VHDL/1. How to use Loop and Exit in VHDL.mp4 32.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/8. Write Your First VHDL Code/2. Test Hello World Code.mp4 31.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/12. While Loop in VHDL/2. Test While Loop in VHDL.mp4 27.1 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/2. VHDL/1. What is VHDL.mp4 24.4 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/16. Sensitivity List in VHDL/2. Test Sensitivity List in VHDL.mp4 23.3 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/11. For-Loop in VHDL/1. How to use For-Loop in VHDL.mp4 21.9 MB
[TutsNode.com] - Get Started with VHDL Programming Design Your Own Hardware/9. Time delay in VHDL/1. How to add a time delay in VHDL.mp4 20.6 MB

猜你喜欢： Own VHDL Get Started Programming Hardware Design Your

【影视】 FPGA Development in VHDL - Beyond the Basics

收录时间:2017-07-06 文档个数:91 文档大小:541.2 MB 最近下载:2025-05-16 人气:6161 磁力链接

03.Working with Custom Data Types/09.Summary.srt 832 Bytes
07.Testing Your Designs/05.Summary.srt 1.0 kB
04.Monitoring Signal States with Attributes/01.Overview.srt 1.1 kB
06.Constructing State Machines/07.Summary.srt 1.1 kB
07.Testing Your Designs/01.Overview.srt 1.1 kB
04.Monitoring Signal States with Attributes/06.Type Kind Attributes.srt 1.1 kB
06.Constructing State Machines/03.State Machine Types.srt 1.2 kB
03.Working with Custom Data Types/01.Overview.srt 1.3 kB
04.Monitoring Signal States with Attributes/02.What Are Attributes.srt 1.4 kB
06.Constructing State Machines/01.Overview.srt 1.4 kB
05.Keeping Code Organized with Subprograms and Packages/07.Summary.srt 1.4 kB
02.Developing for the FPGA/02.Module Overview.srt 1.5 kB
03.Working with Custom Data Types/04.Subtypes.srt 1.5 kB
05.Keeping Code Organized with Subprograms and Packages/01.Overview.srt 1.5 kB
02.Developing for the FPGA/08.Summary.srt 1.5 kB
04.Monitoring Signal States with Attributes/08.Summary.srt 1.7 kB
03.Working with Custom Data Types/05.Multidimensional Arrays.srt 1.8 kB
01.Course Overview/01.Course Overview.srt 2.0 kB
06.Constructing State Machines/02.What Is a State Machine.srt 2.2 kB
03.Working with Custom Data Types/06.Record Types.srt 2.6 kB

猜你喜欢： Development Basics Beyond VHDL FPGA

【影视】 Getting Started with FPGA Programming with VHDL

收录时间:2017-07-03 文档个数:109 文档大小:520.8 MB 最近下载:2025-05-15 人气:10517 磁力链接

05.Writing Sequential Code/09.Summary.srt 649 Bytes
04.Introduction to VHDL/07.Summary.srt 995 Bytes
07.Packages and Components/07.Summary.srt 1.1 kB
08.Debugging and Analysis/04.Summary.srt 1.2 kB
08.Debugging and Analysis/01.Overview.srt 1.3 kB
03.Digital Design Primer/08.Summary.srt 1.3 kB
02.FPGA Technology Overview/02.Module Overview.srt 1.4 kB
03.Digital Design Primer/01.Overview.srt 1.4 kB
04.Introduction to VHDL/01.Introduction.srt 1.5 kB
02.FPGA Technology Overview/09.Summary.srt 1.6 kB
03.Digital Design Primer/07.Logic Element.srt 1.6 kB
06.Writing Concurrent Code/06.Clocks.srt 2.1 kB
07.Packages and Components/01.Overview.srt 2.1 kB
06.Writing Concurrent Code/08.Summary.srt 2.2 kB
08.Debugging and Analysis/05.Course Summary.srt 2.2 kB
03.Digital Design Primer/02.Boolean Logic.srt 2.6 kB
02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.srt 2.7 kB
03.Digital Design Primer/06.Clocks and Timing.srt 2.9 kB
01.Course Overview/01.Course Overview.srt 2.9 kB
05.Writing Sequential Code/02.Signals.srt 3.2 kB

猜你喜欢： Started Programming VHDL FPGA Getting

【影视】 [udemy] Xilinx Vivado Beginners Course to FPGA Development in VHDL [MyFOM]

收录时间:2017-02-10 文档个数:15 文档大小:483.8 MB 最近下载:2025-05-16 人气:3338 磁力链接

MyFreeOnlineMovies.co.uk.html 189.0 kB
Section 1 Introduction to Vivado/How to Download and Install Xilinx Vivado Design Suite.mp4 42.2 MB
Section 1 Introduction to Vivado/Introduction.mp4 16.9 MB
Section 2 Lab 1/Coding and Simulating Simple VHDL in Vivado.mp4 36.2 MB
Section 2 Lab 1/Downloading the Bit-stream to the FPGA.mp4 48.5 MB
Section 2 Lab 1/Implementation of VHDL Design in Vivado and IO Pin Planning.mp4 72.5 MB
Section 2 Lab 1/Introduction to the Vivado Design Suite Interface and Creating a New Project.mp4 47.8 MB
Section 3 Lab 2/Design a Block RAM in IP Integrator.mp4 53.0 MB
Section 3 Lab 2/Simulating BRAM memory IP in Vivado.mp4 23.3 MB
Section 4 Lab 3/Designing a Microblaze Soft Processor in Vivado IP Integrator.mp4 62.0 MB
Section 4 Lab 3/Generating a Microblaze using TCL commands in Vivado.mp4 21.1 MB
Section 4 Lab 3/Learn VHDL by Example.mp4 60.0 MB
Section 4 Lab 3/New Text Document.txt 52 Bytes
Section 5 Conclusion and Bonus Section/Sorry the files are deleted bare with me.txt 51 Bytes
Torrent Downloaded from Glodls.to.txt 237 Bytes

猜你喜欢： Development VHDL FPGA Course udemy Beginners Vivado Xilinx MyFOM

【影视】 VHDL-Intro-1.flv

收录时间:2017-02-27 文档个数:1 文档大小:120.6 MB 最近下载:2024-12-12 人气:8 磁力链接

VHDL-Intro-1.flv 120.6 MB

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