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【压缩文件】 [ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 1 - Verilog.zip

收录时间:2021-03-19 文档个数:1 文档大小:413.1 MB 最近下载:2025-05-14 人气:3873 磁力链接

[ FreeCourseWeb.com ] Udemy - FPGA Embedded Design, Part 1 - Verilog.zip 413.1 MB

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【影视】 [ TutPig.com ] Udemy - Digital Systems and Logic Design with verilog codes

收录时间:2022-05-06 文档个数:29 文档大小:771.0 MB 最近下载:2025-05-14 人气:2119 磁力链接

~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/8 - The MAP method.mp4 98.7 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/6 - Canonical And Standard Form.mp4 91.1 MB
~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/9 - Four value K-Map.mp4 72.1 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/4 - Basic Theorems and properties of Boolean Algebra.mp4 63.5 MB
~Get Your Files Here !/4 - Combinational logic/14 - Full Adder.mp4 59.3 MB
~Get Your Files Here !/4 - Combinational logic/15 - Full Subtractor.mp4 54.9 MB
~Get Your Files Here !/4 - Combinational logic/16 - Decoder.mp4 49.6 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/5 - Digital Circuits implement using Boolean Functions.mp4 38.6 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/7 - Digital logic Gates(AND,OR,NOT,XOR,XNOR,NOR,NAND).mp4 37.9 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/3 - Two Value Boolean Algebra.mp4 33.6 MB
~Get Your Files Here !/4 - Combinational logic/18 - MUX.mp4 31.3 MB
~Get Your Files Here !/4 - Combinational logic/17 - Encoder.mp4 28.6 MB
~Get Your Files Here !/4 - Combinational logic/13 - Half Adder.mp4 21.7 MB
~Get Your Files Here !/3 - K-MAP , SIMPLIFICATION AND MINIMIZATION OF BOOLEAN FUNCTIONS/10 - Don't Care Conditions.mp4 21.1 MB
~Get Your Files Here !/4 - Combinational logic/11 - Introduction of combinational circuits.mp4 18.8 MB
~Get Your Files Here !/2 - Boolean Algebra And Logic Gate/2 - Basic Definitions.mp4 15.9 MB
~Get Your Files Here !/1 - Start Here/1 - Introduction of Digital Systems.mp4 11.7 MB
~Get Your Files Here !/5 - Verilog HDL/21 - Full subtractor verilog code.mp4 7.4 MB
~Get Your Files Here !/5 - Verilog HDL/19 - Half adder verilog code.mp4 3.8 MB
~Get Your Files Here !/5 - Verilog HDL/23 - Encoder verilog code.mp4 2.9 MB

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【影视】 [ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification

收录时间:2022-02-11 文档个数:421 文档大小:3.6 GB 最近下载:2025-05-12 人气:6214 磁力链接

~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4 118.4 MB
~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4 114.0 MB
~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4 108.0 MB
~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4 81.8 MB
~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4 73.4 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4 62.3 MB
~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4 53.5 MB
~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4 53.3 MB
~Get Your Files Here !/1. Introduction/2. Course overview.mp4 52.9 MB
~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4 52.3 MB
~Get Your Files Here !/1. Introduction/1. Welcome!.mp4 45.8 MB
~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4 44.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4 41.9 MB
~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4 41.7 MB
~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4 40.9 MB
~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4 40.5 MB
~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4 39.5 MB
~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4 39.1 MB
~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4 38.5 MB
~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4 38.0 MB

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【压缩文件】 [ FreeCourseWeb.com ] Udemy - Verilog Quick Revision and FAQs.zip

收录时间:2021-04-10 文档个数:1 文档大小:229.1 MB 最近下载:2024-12-13 人气:100 磁力链接

[ FreeCourseWeb.com ] Udemy - Verilog Quick Revision and FAQs.zip 229.1 MB

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【文档书籍】 verilog

收录时间:2017-02-26 文档个数:509 文档大小:157.2 MB 最近下载:2024-10-16 人气:207 磁力链接

FPGA PROTOTYPING with verilog examples - spartan3-2008.pdf 18.8 MB
Digital Design - An Embedded Systems Approach Using Verilog.pdf 2.1 MB
FSM-Based Digital Design Using Verilog HDL.rar 3.4 MB
ch3_Timing_Overhead.pdf 916.1 kB
271clockingnotes.pdf 112.3 kB
blocking and non blocking.pdf 70.3 kB
Boston_FullParallelCase.pdf 74.1 kB
Springer - SystemVerilog for Verification.pdf 1.5 MB
(ebook) Electronics - Verilog Digital Design Synthesis.pdf 11.6 MB
Cadence Verilog Languaje and Simulation Course.pdf 2.1 MB
CummingsHDLCON2001_Verilog2001_rev1_3.pdf 67.8 kB
design through verilog - IEEE.pdf 2.3 MB
eBook.Verilog.VHDL.Golden.Reference.Guide.pdf 377.3 kB
IEEE_Standard_verilog_std_1364_1995.pdf 1.8 MB
Kluwer.Academic.The.Verilog.Hardware.Description.Language.Fifth.Edition.pdf 8.1 MB
Kluwer-_Digital_Computer_Arithmetic_Datapath_Design_Using_Verilog_HDL.pdf 631.6 kB
Principles of Verifiable RTL Design-verilog.pdf 2.1 MB
the_complete_verilog_book.pdf 6.3 MB
Verilog-2001_paper.pdf 209.3 kB
verilog blocking and non blocking.pdf 70.3 kB

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