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磁力管家

BT种子名称

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BT种子基本信息

  • 种子哈希:92d5c07d5d1b3fa8e6169476d4e48b9e22360c41
  • 文档大小:1.1 GB
  • 文档个数:154个文档
  • 下载次数:16832
  • 下载速度:极快
  • 收录时间:2017-02-08
  • 最近下载:2025-05-16
  • DMCA/屏蔽:DMCA/屏蔽

下载磁力链接

magnet:?xt=urn:btih:92D5C07D5D1B3FA8E6169476D4E48B9E22360C41magnet:?xt=urn:btih:92D5C07D5D1B3FA8E6169476D4E48B9E22360C41
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FPGA_HDL_Books的二维码

文档列表

  • pdfArticles/DESIGN AND IMPLEMENTATION OF OFDM TRANSMITTER AND RECEIVER ON FPGA HARDWARE .pdf 5.1 MB
  • pdfArticles/An FPGA-Based Software Defined Radio Platform for the 2.4GHz ISM Band.pdf 4.6 MB
  • pdfArticles/Sensorless speed control of Induction Motor using VHDL.pdf 2.8 MB
  • pdfArticles/fundamentals of digital logic with VHDL design solutions manual.pdf 1.8 MB
  • pdfArticles/A Rapid Prototype Design to Investigate the FPGA Based DTC Strategy Applied to the Speed Control of Induction Motor.pdf 1.8 MB
  • PDFArticles/Introduction to CPLD and FPGA Design.PDF 1.0 MB
  • pdfArticles/Introduction to VHDL.pdf 617.1 kB
  • pdfArticles/FFT, Realization and Implementation in FPGA.pdf 536.8 kB
  • pdfArticles/Моделирование цифровых и микропроцессорных систем. Язык VHDL (Дьяков).pdf 422.8 kB
  • docArticles/Стиль Программирования на Языке Verilog и Руководящие Указания по Программированию.doc 316.4 kB
  • docArticles/Verilog - Инструмент Разработки Цифровых Электронных Схем.doc 236.5 kB
  • pdfArticles/Simulink, Matlab-to-VHDL Route for Full-Custom, FPGA Rapid Prototyping of DSP Algorithms.pdf 197.6 kB
  • pdfArticles/VHDL & Verilog Compared & Contrasted.pdf 47.4 kB
  • pdfArticles/Verilog - accelerating digital design (Gerard Blair).pdf 39.5 kB
  • pdfEng/Verilog HDL - A Guide to Digital Design and Synthesis (Palnitkar)/Part1.pdf 5.6 MB
  • pdfEng/Verilog HDL - A Guide to Digital Design and Synthesis (Palnitkar)/Part2.pdf 3.9 MB
  • pdfEng/Verilog HDL - A Guide to Digital Design and Synthesis (Palnitkar)/Part3.pdf 2.1 MB
  • jpgEng/Verilog HDL - A Guide to Digital Design and Synthesis (Palnitkar)/Cover_1.jpg 421.6 kB
  • pdfEng/Digital signal processing with Field Programmable Gate Arrays (Uwer Meyer-Baese).pdf 68.5 MB
  • pdfEng/HDL Chip Design. A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog (Douglas Smith).pdf 40.6 MB
  • ==查看完整文档列表==

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